基于FPGA的復(fù)數(shù)浮點(diǎn)協(xié)方差矩陣實(shí)現(xiàn)

摘 要:基于FPGA的協(xié)方差矩陣運(yùn)算的實(shí)現(xiàn)大多采用的是定點(diǎn)計(jì)算方式，在運(yùn)算過程中，存在數(shù)據(jù)處理動(dòng)態(tài)范圍小，容易溢出，截?cái)嗾`差等問題。加之以空間譜估計(jì)為研究背景的協(xié)方差矩陣運(yùn)算，大多得到的是針對(duì)特殊陣列模型的實(shí)對(duì)稱矩陣，不具備通用性。針對(duì)定點(diǎn)運(yùn)算的不足和該運(yùn)算的適用范圍，研究了浮點(diǎn)運(yùn)算和復(fù)數(shù)運(yùn)算的特點(diǎn)，提出了基于復(fù)數(shù)矢量的浮點(diǎn)協(xié)方差運(yùn)算的FPGA實(shí)現(xiàn)方案。在Altera\\\\ stratix \\\\EP1S20F780C7中的仿真和調(diào)試結(jié)果表明了該方案的有效性。

關(guān)鍵詞:協(xié)方差矩陣運(yùn)算; 浮點(diǎn)運(yùn)算; 復(fù)數(shù)運(yùn)算; FPGA

中圖分類號(hào):TN919; TP302文獻(xiàn)標(biāo)識(shí)碼:A

文章編號(hào):1004-373X(2010)15-0121-04

Realization of Complex Floating-point Covariance Matrix Operation Based on FPGA

WEI Yu-mei， LIU Shuai， JIN Ming

(Harbin Institute of Technology， Weihai 264209， China)

Abstract: The covariance matrix operation based on FPGA is realized with the fix-point calculation mode mostly， but there are some problems in the computing process， such as small dynamic range of data processing， easy overflowing， truncation error and so on. Additionally， covariance matrix operation that takes the spatial spectrum estimation as the research background mostly gets the real symmetric matrix which is in connection with special array model， and does not have universality. To direct at the shortness and application scope of the fixed-point operation， and implementing scheme of complex floating-point covariance matrix operation based on FPGA is put forward after the study on the characteristics of the floating point operation and complex operation. The results of simulation and debugging on EP1S20F780C7 indicate that the scheme is effective.

Keywords: covariance matrix operation; floating-point arithmetic; complex arithmetic; FPGA

0 引 言

協(xié)方差矩陣的計(jì)算是信號(hào)處理領(lǐng)域的典型運(yùn)算，是實(shí)現(xiàn)多級(jí)嵌套維納濾波器、空間譜估計(jì)、相干源個(gè)數(shù)估計(jì)以及仿射不變量模式識(shí)別的關(guān)鍵部分，廣泛應(yīng)用于雷達(dá)、聲吶、數(shù)字圖像處理等領(lǐng)域。采用FPGA(Field Programmable Gate Array)可以提高該類數(shù)字信號(hào)處理運(yùn)算的實(shí)時(shí)性，是算法工程化的重要環(huán)節(jié)。但是FPGA不適宜對(duì)浮點(diǎn)數(shù)的處理，對(duì)復(fù)雜的不規(guī)則計(jì)算開發(fā)起來也比較困難。故目前國內(nèi)外[1-4]協(xié)方差運(yùn)算的FPGA實(shí)現(xiàn)都是采用定點(diǎn)運(yùn)算方式。

在所有運(yùn)算都是定點(diǎn)運(yùn)算的情況下，每次乘法之后數(shù)據(jù)位寬都要擴(kuò)大一倍。若相乘后的數(shù)據(jù)繼續(xù)做加減運(yùn)算，為了保證數(shù)據(jù)不溢出，還必須將數(shù)據(jù)位寬擴(kuò)展一位，而協(xié)方差矩陣的運(yùn)算核心就是乘累加單元，隨著采樣點(diǎn)數(shù)的增加，位寬擴(kuò)展呈線性增加。最終導(dǎo)致FPGA器件資源枯竭，無法實(shí)現(xiàn)設(shè)計(jì)。為了保證算法的實(shí)現(xiàn)，必須對(duì)中間運(yùn)算數(shù)據(jù)進(jìn)行截?cái)啵瑢⒚看卫奂拥慕Y(jié)果除2(可以通過移位運(yùn)算來實(shí)現(xiàn))，以避免溢出。……