0.15~5.8GHz超寬帶多功能鎖相環(huán)設(shè)計

中圖分類號：TN911.8 文獻標志碼：A

Abstract：To meet the demands of communication base stations，radars，and other systems for high spectral purity local oscilator signals，an ultra wideband and multi functional phase-locked loop （PLL）chip was designed and implemented based on the 130 nm SiGe BiCMOS processAn of-chip test circuit system was also designed in conjunction with the chip’sapplication.The digital-controlled charge pump（CP）within the PLL chip can adjust crucial parameters such as loop bandwidth and system power consumption by controling the CP current.The wideband switchable frequency divider divides the fundamental wave signaloutput by voltagecontrolled oscilator （VCO）with diferent operating frequency bands and performance characteristics outside the chip in the feedback loop，achieving alocked output of thefundamental wave signal in the range of 1＼～5.8 GHz.At the same time，an independent frequency division system integrated within the chip further expands the locking bandwidth by dividing the VCO's fundamental wave signal output by1/2/4/8/16，covering the output oflow-frequency signals ranging from 0.15＼～1GHz below the fundamental wave signal band.Tape-out testing of this PLL chip demonstrates a phase noise of -105.8 dBc/Hz at 100kHz within the loop bandwidth for a fundamental wave output of 2.4GHz ，with a reference spur suppression of -86.12 dBc. Powered by 3.3V ，the chip can achieve a maximum phase detection frequency of 75 MHz and operate normally between -55^°C and +85^°C ， providing high spectral purity local oscillator signals.

Key words：phase-locked loop;bandwidth; charge pump;phase noise

現(xiàn)代無線通信、雷達系統(tǒng)、電子對抗等應(yīng)用領(lǐng)域中，鎖相環(huán)（phase-locked loop，PLL）系統(tǒng)起到至關(guān)重要的作用[1-2].鎖相環(huán)作為收發(fā)機系統(tǒng)的關(guān)鍵部件，為調(diào)制和解調(diào)等模塊提供本振信號，而相位噪聲和帶寬作為鎖相環(huán)的關(guān)鍵指標直接影響著整個收發(fā)機系統(tǒng)的性能[3-4].鎖相環(huán)的相位噪聲對收發(fā)機系統(tǒng)高階調(diào)制中的比特誤碼率（biterrorrate，BER）和誤差矢量幅度（errorvectormagnitude，EVM）退化影響較大，限制系統(tǒng)的整體性能[5.根據(jù)香農(nóng)定理，通信速率主要受信道寬度和信噪比兩方面的影響.更寬的信道寬度可以獲得更高數(shù)據(jù)傳輸速率.低相位噪聲、多功能、超寬帶鎖相環(huán)芯片的實現(xiàn)，不僅可以滿足寬帶跳頻的技術(shù)需求，還可以進一步節(jié)省收發(fā)機系統(tǒng)的功耗和成本，實現(xiàn)整個收發(fā)機的小型化、通用化.

如何在確保相位噪聲保持在較低水平、功能保持全面的同時，拓展鎖定帶寬，是一項技術(shù)挑戰(zhàn).文獻[6]設(shè)計的PLL提供了一種正交輸入輸出的分頻器，拓展了鎖定帶寬，但電荷泵無法數(shù)字控制，電流調(diào)節(jié)范圍小，帶有尾管結(jié)構(gòu)的分頻器引入靜態(tài)功耗，整體功耗為 135mW 文獻[7]提出了一種雙回路PLL，其功耗較低，但鎖定帶寬較窄，參考雜散抑制較差，只有 -49.42dBc ，功能較為單一，無法滿足廣泛應(yīng)用需求.文獻[8]提出了一種帶有數(shù)字模擬轉(zhuǎn)換器的PLL，可以克服電源電壓和溫度引起的頻率偏差，但鎖定帶寬較窄，僅為 1.8～2.5GHz ，且?guī)?nèi)噪聲較高.

本文針對超寬帶、低噪聲和靈活應(yīng)用的需求，基于 130nm SiGeBiCMOS工藝提出了一種鎖相環(huán)系……