Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

Yuankang Chen(陳遠(yuǎn)康), Yuanliang Zhou(周遠(yuǎn)良), Jie Jiang(蔣杰),Tingke Rao(饒庭柯), Wugang Liao(廖武剛), and Junjie Liu(劉俊杰)

College of Electronics and Information Engineering,Shenzhen University,Shenzhen 518060,China

Keywords: electrostatic discharge,floating n-well,low-voltage trigger silicon-controlled rectifier

1.Introduction

With the gradual shrinking of the electrostatic discharge(ESD)design window and chip area, the ESD in low-voltage integrated circuits faces many challenges arising from thin dielectrics,shallow junctions,etc.Accordingly,designs of ESD protection are critical for high-performance circuits.[1-4]The commonly used protective devices in ESD protection design include diode,metal-oxide-semiconductor field-effect transistor(MOSFET),bipolar junction transistor(BJT),and siliconcontrolled rectifier (SCR).Among these devices, SCR possesses a relatively higher current driving capability, the highest area efficiency,and robustness.[5]However,a high trigger voltage of common SCR limits its applications in advanced CMOS technology.[6,7]On the other hand,the SCR with a low holding voltage usually faces a latch-up effect.[8,9]Therefore,SCR-based ESD protection devices have been studied over the past few decades.[10-14]To accommodate the ever-shrinking ESD design window, devices with low trigger voltage, high hold voltage, and improved dynamic resistance have become a research hotspot.

Low-voltage trigger silicon-controlled rectifier(LVTSCR) affects the avalanche breakdown by introducing the GGNMOS structure in the SCR, as shown in Fig.1(a).The improved device structure can significantly reduce the trigger voltage of SCR.However, the low holding voltage caused by the strong snapback of the coupled n-p-n and pn-p bipolar junction transistors(BJT)has not been optimized in traditional LVTSCRs.[15,16]The traditional approach is to increase the holding voltage by increasing the gate length.However,this improvement increases the area of the thin gate oxide, resulting in a drop in secondary breakdown current.The N+active region bridged on the P/N well junction of the LVTSCR is divided into blocks.This improved method will build an auxiliary current discharge path, which can increase the holding voltage.[17]However,this method will reduce the failure current value and affect the robustness of the device.

In this work,a novel structure named as the PN-LVTSCR is proposed by adding a floating n-well region and ESD implant to the LVTSCR structure.The simulation results show that the use of floating n-well and ESD implant in the LVTSCR maintains the low trigger voltage characteristics and simultaneously increases the holding voltage.

2.A novel low voltage trigger silicon-controlled rectifier

2.1.Device structure and description

The cross-sectional and equivalent circuit diagrams of the conventional LVTSCR and the proposed PN-LVTSCR are shown in Fig.1.The width of the conventional LVTSCR and the proposed PN-LVTSCR is set to be an identical value of 100μm.The other key dimension parameters are outlined in Table 1.

For the LVTSCR, the equivalent circuit diagrams are composed of a parasitic p-n-p transistor (pnp), lateral n-pn transistor (npn), n-well resistance (RNW), p-well resistance(RPW), and a GGNMOS path.The structure of the LVTSCR is characterized by the GGNMOS structure embedded in the traditional SCR.The addition of the highly doped N+region of GGNMOS will reduce the avalanche breakdown voltage,thereby accelerating the triggering process of the LVTSCR.

Table 1.Key device parameters of the conventional LVTSCR and the proposed PN-LVTSCR.

Fig.1.Cross-sectional and equivalent circuit diagrams of (a) the LVTSCR and(b)the PN-LVTSCR.

2.2.Mechanistic analysis of the proposed device

To verify the ESD protection characteristics of the PNLVTSCR, device simulations were conducted using Sentaurus TCAD.[18]All results simulated are based on the 0.18-μm CMOS process.The multi-current pulses with a rise time of 10 ns and a width of 100 ns to mimic human body model(HBM)events are applied to devices.The quasi-statistic characteristics are obtained by averaging the transient data in an interval of 60-90 ns.[19,20]The physics models such as mobility,avalanche breakdown, Shockley read hall, Auger recombination, effective intrinsic density, and Fermi energy are utilized in these simulations.Lattice temperature correlates with device failure in simulations,and the critical failure temperature of the device is defined in this paper as 1200 K,and the doping concentrations and depths for different regions are listed in Table 2.

Table 2.The doping concentrations and depths for different regions.

The distribution of total current density during the whole triggering process of the PN-LVTSCR is shown in Fig.2.When the anode voltage is too low,there is almost no current flow inside the device.At this time,discharge current does not occur for the PN-LVTSCR,as shown in Fig.2(a).

The GGNMOS will be the first one to turn on when the ESD surge reaches the GGNMOS avalanche breakdown threshold,as shown in Fig.2(b).The current path at this time is used as the main discharge path(path 1).However,the floating n-well reduces the doping concentration of the drain region of the GGNMOS.[21,22]This affects the avalanche breakdown process,and increases the value of trigger voltage(Vt).

Fig.2.The total current density distribution of the PN-LVTSCR with(a)no current discharge path,(b)GGNMOS turned on,and(c)parasitic SCR triggered.

As shown in Fig.1(b), the novel device structure introduces an additional floating n-well (FN) under the drain of GGNMOS.Meanwhile,an ESD implant(P-ESD)is employed in the region close to the source.The main purpose of introducing floating n-well and ESD implant is to reduce the current flowing into the SCR current path and to weaken the beta value of the parasitic n-p-n transistor(npn2).

Figure 2(c) shows that when the GGNMOS is turned on, the internal cross-coupling n-p-n transistor and the pn-p bipolar transistor will induce current positive feedback.Namely,the current in the base area is continuously amplified,and a large current is generated.High voltage is no longer needed inside the device to maintain the avalanche breakdown state,causing the conductance modulation effect.As the space charge near the avalanche junction disappears, snapback occurs in the device.At this point, the SCR path is turned on,and the PN-LVTSCR starts to work.Notice that the introduction of a floating n-well and an ESD implant will increase the base width and base doping concentration of the npn2.This improved method can significantly enhance the current discharge capability of path 1,decrease the beta value of the npn2transistor,and reduce the current flowing through the SCR current path (path 2).Accordingly, the current gain of the SCR is weakened and requires a higher holding voltage to maintain the conduction of the SCR.

Figure 3 shows theI-Vcurves of the traditional LVTSCR and the PN-LVTSCR,where the lengths ofD1,D2,andD3are 3 μm, 0.5 μm, and 2 μm, respectively.The holding voltage(Vh) of the proposed PN-LVTSCR is increased from 4.37 V to 5.53 V compared with the traditional one, equivalent to a growth rate of 28.6%.

Fig.3.The I-V curve of the traditional LVTSCR and the proposed PNLVTSCR, where the sizes of D1, D2, and D3 are 3 μm, 0.5 μm, and 2μm,respectively.

On the other hand, a secondary breakdown occurs when the current is eventually increased to the point of thermal failure of the device.However, the introduction of ESD implant affects the operation of the parasitic N+/P junction, and enhances the current flowing through path 1,thus improving the overall current discharge capability of the device.Such an influence by using ESD implant can also be utilized to understand the improved secondary breakdown(It2)current.

3.Results and optimizations

The ESD protection performance of the proposed PNLVTSCR with varying parameters is shown in Fig.4.

The influence ofD1on ESD performance is discussed when theD2length is 0.5μm and theD3length is 2μm.Figure 4 shows theI-Vcurves of the LVTSCR and PN-LVTSCR with differentD1lengths.As the length ofD1increases, the trigger voltage of the PN-LVTSCR slightly increases compared to the LVTSCR.The main reason for this phenomenon is that the floating n-well reduces the doping concentration of the drain region of the GGNMOS,which affects the avalanche breakdown of the n+/p-well.Although the trigger voltage has increased,the voltage range is still maintained at 7-8 V,which meets the design requirements of ESD protection for the lowvoltage integrated circuit.

Fig.4.The I-V curve of the traditional LVTSCR and the proposed PN-LVTSCR,for different D1 values.

Similarly,the holding voltage of the same type of device continues to rise with increasingD1.The rise ofD1causes the base width of npn2to be elongated,which affects the current gain of the transistor.The result requires a larger holding voltage to maintain the internal SCR current path open.

The PN-LVTSCR with the sameD1length has a higher holding voltage compared with the LVTSCR.It is mainly attributed to the combined effect of the floating n-well and the ESD implant.In such a PN-LVTSCR, the positive feedback effect in the SCR current path is weakened, and the current flowing through the SCR path becomes lower.To maintain the conduction of the SCR path,a larger holding voltage is required.WhenD1is 3μm,and the depth of the floating n-well is the same as the n/p well, the holding voltage and trigger voltage reach 5.53 V and 7.56 V,respectively.Therefore, the PN-LVTSCR can be used as an ESD protection device for ICs operating at 5 V.It is worth mentioning that this implementation method weakens the positive feedback of the SCR and concurrently slowdowns the device’s response speed.

The figure of merit (FOM) is usually used as an evaluation index to evaluate the ESD protection performance of the device.[23]The definition of FOM is as follows:

whereAis the total silicon area of the ESD protection device.The performance parameters of the traditional LVTSCR and the PN-LVTSCR with different structure sizes are listed in Table 3, including trigger voltage, holding voltage, secondary breakdown current,and total silicon area.Finally,the FOM of each device is obtained by calculation.From Table 3,it can be seen that the ESD protection design of this improved LVTSCR has the most efficient FOM.

Table 3.The electrostatic characteristics of the LVTSCR and the PN-LVTSCR.

Figure 5 shows the effect of different depth of well(D4)values on the ESD protection performance of the device,

where the sizes ofD1,D2,andD3are 3μm,1μm,and 0μm,respectively.

As the depth of the well increases,the trigger voltage rises from 6.9 V to 7.2 V,and the holding voltage continues to rise from 4.3 V to 5.1 V,with an increase of 19%.The addition of floating n-well weakens the doping concentration of the GGNMOS N+region.This will affect the avalanche breakdown process,causing the trigger voltage to rise.On the other hand,the length of the base region of the npn2transistor is extended,which weakens the positive feedback effect of the thyristor,thereby increasing the holding voltage.

Fig.5.The I-V curve of the traditional LVTSCR,when taking different D4 values.

Fig.6.The I-V curves of the traditional LVTSCR with different lengths of D3.

The ESD implant plays a critical role in the PN-LVTSCR.The influence of the length of ESD implant on ESD performance is further explored.For the parameter setting, the length ofD1is optimized at 3 μm, and no floating n-well is added.TheI-Vcurves of the PN-LVTSCR with different ESD implant lengths are shown in Fig.6.

With an increase in ESD implant length,the trigger voltage shows little change while the holding voltage is significantly enhanced.Due to the introduction of the ESD implant,the base doping concentration of the parasitic transistor of the GGNMOS is increased.This causes the avalanche breakdown of the PN-LVTSCR to occur earlier,but this improvement does not affect the trigger voltage.The main reason for this phenomenon is that the ESD implant reduces the amplification factor of the internal positive parasitic npn transistor,a larger voltage is required to establish the internal positive feedback.At the same time,the doping concentration of the base region of the n-p-n transistor in the SCR current path has also been enhanced,thereby increasing the holding voltage.

4.Conclusion and perspectives

In summary, we have proposed a novel LVTSCR device with a floating n-well and an ESD implant.It shows a better electrical characteristics compared with traditional LVTSCRs in terms of the holding voltage.With a parameter setting ofD1,D2, andD3at 3 μm, 0.5 μm, and 2 μm respectively, the trigger voltage is maintained at 7.56 V,and the holding voltage exceeds 5.53 V,fulfilling the ESD protection requirements of 5 V low-voltage integrated circuits and holding the potential to implement an ESD protection operation within a tiny window of 2.03 V.

Acknowledgements

The authors thank the Semiconductor Device and Integrated Circuit Reliability Laboratory at Shenzhen University for providing theoretical guidance and technical support.

Project supported by the National Natural Science Foundation of China(Grant No.61904110)