Design on Front-end Readout ASIC with Variable Gain and Wide Dynamic Range for 3D Si PIN Array Thermal Neutron Detector

HAN Ning, LI Long, LI Xinzan, LIU Shuhuan,*, MA Yong, XIONG Yanli, LI Bingjun, ZHANG Guohe, Carlo Ettore Fiorini, CHEN Wei

(1.School of Energy and Power Eneineering, Xi’an Jiaotong University, Xi’an 710049, China; 2.School of Information Technology, Hebei University of Economics and Business, Shijiazhuang 050061, China; 3.School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China; 4.Department of Electronic Information and Bioengineering, Politecnico di Milano, Milan 20133, Italy; 5. Northwest Institute of Nuclear Technology, Xi’an 710024, China)

Abstract: The front-end readout ASIC based on Si CMOS technology is primarily designed according to the output signal characteristics of the 3D Si PIN array thermal neutron detector. The key circuit modules of the designed readout ASIC include the charge sensitive amplifier (CSA), the analog switch design, an automatic gain control module (AGC) with three-level charge sensitivity automatic switching, the correlation dual sampling (CDS) and reference current source circuit. The simulation results show that the input dynamic range of the front-end circuit is 10 fC-8.0 pC. The three gain coefficients of the designed ASIC according to the thermal neutron detector output signal characteristics are set as 1.9 V/pC, 0.39 V/pC and 94 mV/pC, respectively. The integral nonlinearity of the designed ASIC is less than 1%. The single channel static power consumption is about 5.36 mW. The equivalent noise charge at zero input detector capacitance is 241.6e-. The counting rate can arrive to the level of 1 MHz.

Key words：front-end readout circuit; wide dynamic range; charge sensitive preamplifier

1 Introduction

For improving the detection efficiency and neutron, gamma discrimination on traditional planar semiconductor neutron detector, the new structure 3D semiconductor neutron spectrum measurement array detector with optimized high detection efficiency and high ratio of neutron, γ ray discrimination has become a hot research field at home and abroad[1-10]. In the past few years, the domestic research and development of this type of Si array detector were designed with discrete devices. However, its integration is low, power consumption is high, and the spatial resolution is not high. It is well known that the neutron radiation field is usually accompanied by photon, and the output pulse current (that is integral charge) signal of the detector has a wide response dynamic range, whose dynamic range may be in fC-pC, and may span 3-5 orders of magnitude, depending on the intensity of the radiation field and energy spectrum distribution characteristics. Therefore, based on modern integrated circuit technology, we design a wide-dynamic, high-integration front-end readout circuit, which can be used for setting up the lightweight, low power consumption, high performance thermal neutron detection.

Since 2001, a readout ASIC for detecting electromagnetic shower energy deposition has been designed based on BiCMOS process in CERN, which can maintain a small range of high gain in the calibration mode, and realize the input dynamic range of 4-1600 fC in the operation mode[11]. In 2006, a readout ASIC named CASIS was designed based on 0.35 μm CMOS process in Italian National Institute of Nuclear Physics[12]. The CSA realized switch between 0-2.5 pC and 0-50 pC input charge using a real-time automatic gain selection circuit. Since 2012, Wang et al.[13]designed a 4-channel front-end ASIC, each channel includes the CSA, charge gain stage, and CR-(CR)4filter. The range of the input signal is 2-350 fC, the ENC is less than 1000e-. Recently, a 4-channel filter shaping chip based on 0.35 μm CMOS process has been designed[14]. The power consumption of 6.6 mW/channel was obtained. Through investigation and comparison, it is found that there is still a big gap between domestic and foreign research in the front-end readout circuit of the radiation detector. The automatic adjustment of gain is still in a relatively vacant state. The contradiction between the dynamic range and the gain still needs to be resolved.

In this paper, a front-end readout ASIC in CHRT 0.18 μm mixed Si CMOS technology is presented to achieve variable gain and wide dynamic range. In this application, the range of the input signal is 10 fC-8.0 pC, and the equivalent noise charge (ENC) is about 241.6e-/channel under zero input detector capacitance.

2 Design requirements

2.1 Detector

Planar neutron detectors have a big limit that is less than 5% detection efficiency. Well, by creating three-dimensional microstructures such as inclined grooves or column holes in the detector and filling them with neutron conversion materials, the detection efficiency can be improved to about 35%[15]. The latest research shows that the detection efficiency of the double-sided silicon microstructure array detector is effectively improved compared to the single-sided Si microstructure detector. The detailed analysis of this detector can be found in reference [11]. However, the complexity of the double-sided microstructure process increases, which may be weaker than the single-sided microstructure detector in terms of mechanical properties and product yield. On the other hand, judging from the distribution characteristics of the sensitive area, the unit structure is still a flat PIN detector, and the spatial resolution is relatively poor. In order to overcome the above shortcomings, our research group proposed a new 3D structure Si PIN high-efficiency array detector model. The 3D Si PIN array detector spatial resolution is expected to tens of microns-100 microns with the designed 3D electrodes and the embedded thermal neutron converter in bulk silicon. The n+and p+electrode and the thermal neutron converter are processed with DRIE technology. Furthermore, the detector depletion voltage can be decreased and the current pulse width generated by the neutron nuclear reaction can be reduced (it is expected to be reduced to ns order), the charge collection time will be reduced and the thermal efficiency (CCE) can be improved.

The output characteristics of detector[16]include signal polarity, spatial resolution, signal frequency, signal amplitude and frequency band, detector capacitance, leakage current, etc., and the last three are focused on in the design of the front-end readout chip. The output signal amplitude of the detector is related to the charge collection time, which affects the working frequency of the detector. The detector capacitance limits the speed of the circuit and affects the noise level of the entire circuit. Its value varies greatly depending on the type of detector technology, and can range from several fF to nF. For Si array detectors, the size is approximately on the order of a few pF. The detector output signal is simplified as a pulse current source with a certain width in parallel with a capacitor, as shown in Fig.1. The current source is equivalent to the charge signal output by the detector, and the parallel capacitance represents the output capacitance of the detector.

2.2 Selection of preamplifier

Three types of the preamplifiers including the current sensitive amplifier, the voltage sensitive amplifier, and the charge sensitive amplifier are considered as the candidates of core circuit. Comparing the characteristics of the different preamplifiers, the stability of the charge amplifier is better than the other two. The most obvious advantage is that the detector capacitance has no influence on the amplitude of the charge amplifier output voltage. The voltage amplitude is only affected by the input charge and the feedback capacitance.

Fig.1 Detector equivalent circuit model (a) and simplified detector output current pulse signal (b)

2.3 Design index

A variable gain readout ASIC with three-stage gain conversion was designed for Si array neutron detector. The maximum detector capacitance is 10 pF. According to reference [2], when the α (2.05 MeV) and T (2.73 MeV) produced by the thermal neutron nuclear reaction are all deposited in the detector pixel sensitive region and the charge collection efficiency (CCE) is 100%, the maximum valueQmaxof the ionized charge generated will near to be:

(1)

Where,Nrepresents an integer,estands for elementary charge, and its value is 1.60×10-19,Edepis particle energy deposition in detector sensitive region (MeV),EαandETare the full energy deposition of α or T in detector sensitive region (MeV), respectively,Wis the mean ionization energy of silicon material (3.6 eV).

Similarly, the maximum ionization charge quantities generated approximately 9.0 fC (or 12.0 fC), if only the full energy of α (or T) is deposited in the sensitive region of the detector. When the amounts of the 3D Si PIN pixels of the processed array detector is processed larger than 1000 and the CCE of each pixel is near to 100%, the accumulated ionizing charge quantity output from all pixels will arrive to pC. According to the output signal characteristics of the detector and requirements, a preliminary design index for the front-end ASIC designed is listed in Table 1.

Table 1 Index required for designed readout ASIC

3 Proposed front-end ASIC model

According to the above description, the overall frame of the front-end readout circuit is shown in the Fig.2. The main function modules include the detector equivalent circuit, the charge sensitive amplifier (CSA), an automatic control module (AGC) designed for gain conversion, a correlation dual sampling module (CDS), and a reference current source circuit.

The detector equivalent circuit model includes an ideal current signal source in parallel with a capacitor. The influence of the leakage current on the circuit is ignored in the modeling, because the detector leakage current in the circuit is much smaller than the ionization pulse under the low bias voltage and can be deduced by the AC coupling mode.

Fig.2 Block diagram of variable gain front-end readout circuit

AGC is designed to control the charge sensitive preamplifier gain conversion. It will control the switch to the higher gain stage when the CSA input charge is low. In contrary, it will control the CSA convert to the low gain stage when the input charge is high to ensure the output swing not reaching to the saturation state.

Since the equivalent input noise is mainly composed of 1/f(fis the frequency) noise under CMOS technology, increasing the channel area can reduce this type of noise. However, the large-scale arrays require the smallest possible circuit area. Considering the limits described above, it is very necessary to set up the filter circuit after the pre-amplifier while increasing the input transistor area as much as possible.

4 Key circuit modules

4.1 CSA core

The tradeoff of noise performance, power dissipation and dynamic input range is necessary for the selection of the type of the CSA core. According to the design requirements (like high gain, low noise and power dissipation), pre-amplifier adopts a single-ended input cascode structure in general. On the one hand, as the transconductance of the input transistor is still limited, then further considering other factors related with the dynamic input range, voltage output swing and feedback connection mode, the folded cascode is finally chosen. For another, in the actual manufacturing process, the PMOS is placed in the N-WELL of the same substrate, which is beneficial to isolate the noise of the substrate, and the flicker noise of the PMOS is lower than that of the NMOS tube, so PMOS is selected as the input tube. The detailed analysis of this choose can be found in reference [17] and [18]. Thus, a single-ended that cascode amplifier with a PMOS as the input transistor is adopted to implement the CSA core. The schematic is shown in Fig.3. The DC gain and gain-bandwidth production (GBW) of a CSA is given as:

Adc=gm,eqRp2,GBW=gm,eq/2πCp2

(2)

Fig.3 Circuit module of CSA core

The AC simulation results of the CSA are shown in Fig.4. It can be seen that the DC gain is 70.41 dB, the phase margin is 51.15°, and the unity gain bandwidth is 493.7 MHz. What’s more, the magnification is high and the bandwidth is large, which meet the design requirements. The transient simulation results of this single-ended amplifier are shown in Fig.5. The output signal can follow the input well, except there is a 64 ns delay.

Fig.4 Result of folded cascode AC simulation

4.2 Analog switch module

The performance of the switches, as an essential part of the circuit, has direct impacts on the amplifier output characteristics. Compared with bipolar technology, CMOS switch has simple structure and small error, so it is widely used in switched capacitor circuits. In this work, the designed switch module is based on CMOS structure. It is found that NMOS devices cannot follow the input signal quickly due to the slow change speed when transmitting high voltages. However, for complementary PMOS, there is no problem when transmitting high voltages, so the two can be combined.

Fig.5 Transient simulation result of CSA

The design of the switch mainly considers two influence factors including the speed and precision of the switch. A simple and universal speed measurement standard is the time that takes for the output voltage to rise from zero to the maximum input level after the switch is turned on. Since this process takes unlimited time, it can be assumed that the output voltage reaches stability when it is within a certain error range near the final value. The switching precision is mainly influenced by channel charge injection, clock feedthrough andKT/C(Kis the Boltzmann constant,Tis the absolute temperature,Crepresents the value of the capacitor) noise. The tradeoff of speed and precision is necessary for the design of the switch since the effects of the influencing factors on switch speed and accuracy are opposite.

In order to reduce the error, on the one hand, the accuracy deviation caused by the clock feed-through can be compensated respectively by adding ‘virtual switches’ on the left and right sides of the transmission gate. On the other hand, by selecting an appropriate gate width, charge injection and clock feedthrough can be suppressed. The schematic is shown in Fig.6.

Fig.6 Diagram of analog switch

Fig.7 Simulation of analog switch

The switch performance is checked by transient simulation, as shown in Fig.7. The curves from top to bottom stand for the input rectangular signal, clock control signal and output signal, respectively. The input signal shown in the first row has 1 μs delay. Its period is 10 μs, the high level sets as 3 V, the low level is 0 V and the duty cycle is 0.5. The low and high voltage levels setting for the clock signals displayed in the middle row are 0 V and 3.3 V, respectively. In the design, the clock signal is used to control the switch state. When the clock signal’s rising edge coming, the switch is closed, and the output voltage equals to the input voltage. Similarly, when the clock signal’s falling edge coming, the switch is opened. As shown in Fig.7, compared with the switch closed state, the output voltage dropped by 3 mV after the switch is opened, that is, the deviation of the switch output voltage is about 3 mV. This is because the clock feedthrough cannot be completely eliminated. Considering that the load capacitor at the output end is 1 pF, the switching accuracy is relatively accurate in terms of the resolution of the CSA.

4.3 Automatic gain control module

The gain automatic adjustment module designed is divided into two parts: voltage comparator and D flip-flop with reset function. The comparator outputs either a logical high (supply voltage) or a logical low (ground) level by comparing the CSA output to a preset value. As no phase compensation circuit set in the designed module, the stability of the module has to be sacrificed in order to improve a higher speed. The simplified schematic of the comparator is shown in Fig.8, which increase drive capability with one-stage push-pull output. The power supply rejection ratio (PSRR) of the comparator simulated is about 62.78 dB and common mode rejection ratio (CMRR) is about 87.72 dB.

Fig.8 Simplified schematic of comparator

The master-slave D flip-flop is selected to avoid oscillation at the output end of the comparator due to noise interference. Meanwhile, considering that the flip-flop is accompanied by metastable state[19], a matching reset circuit is designed to avoid the occurrence of the third state. The simulation results prove that the function of the designed D trigger is successfully achieved.

4.4 CDS design

For improving the signal-to-noise ratio, the filter circuit is one of the key components of the CSA. The schematic of the correlation double sampling (CDS) is shown in Fig.9. The two-stage amplifier cascade structure is adopted. The stability of the CDS can be im-proved by adding the compensation capacitor Cc. It mainly uses the correlation of noise in time, and filters the relevant noise by subtracting the two samples during integration and reset. Relevant studies[20]have also demonstrated its suppression effect on low-frequency noise. In this paper, it is more appropriate to adopt discrete time filter taking into account the designed pre-amplifier using switch reset and the output is a step signal.Fig.10a displays that the low-frequency gain of the CDS circuit is 84.9 dB, the phase margin is 62.7°, and the unity gain bandwidth is 38.45 MHz when the DC input signal voltage is set as 2 V. What’s more, in the low frequency part (less than 1 kHz), the common mode rejection ratio and power supply rejection ratio are both greater than 80 dB.

Fig.9 Schematic of CDS

Fig.10 AC simulation of CDS (a) and common mode rejection ratio and power supply rejection ratio (b)

The transient simulation results when the input charge is 200 fC are shown in Fig.11. The three lines in Fig.11 from top to bottom are the input pulse current signal, the output voltage of the charge-sensitive preamplifier, and the output voltage of the correlated double sampling, respectively. The reset signal delay is 1 μs, and the pulse width is 1 μs, and the input signal delay is 3 μs. According to the amplitude voltage of the four transient measurement points marked in the simulation results, CDS realizes the function of subtracting the two sampling results.

Fig.11 Transient simulation result of CDS

4.5 Reference current source circuit

The current source used in actual application is realized by the proportional copy of the current mirror to the reference source, not an ideal current source, which main goal is to provide a circuit with a voltage or current that independent of the power voltage supply and temperature. The designed reference source uses self-bias mode. As thus the output current is independent of the reference voltage. The PSRR and temperature coefficient (Tc) given as:

PSRR=dB20[(ΔIref/Iref)/(ΔVDD/VDD)]

(3)

(4)

Where,Irefis the design reference current value, ΔIrefis the current change value,Imaxis the maximum current,Iminis the minimum current,Imeanis the average current,Tmaxis the maximum temperature,Tminis the minimum temperature, VDD is the power voltage and ΔVDD is the voltage change value.

The schematic of the proposed reference current source is shown in Fig.12. It consists of the co-source and gate current mirror structure to makeIrefandIoutequal as much as possible.R1andR2are resistors with positive or negative temperature coefficients designed with N-well resistors and polysilicon resistors. The function of the resistors can regulate the electric current and inhibits the change of the current reference with temperature as well. The designedIrefcurrent level is about 10 μA. The power supply rejection ratio of reference current source circuit is shown in Fig.13. It can be seen from Fig.13 that the power supply rejection ratio is greater than 40 dB in the range of 10 MHz, and the anti-interference ability of the power supply noise is better.

Fig.12 Schematic of reference current source

5 Simulation result and discussion

5.1 Counting rate

The simulation results of the designed front-end readout ASIC response to the counting rate of the detector output signal are shown in Fig.14. The signals displaying in the first row are the defined detector output pulse current signalIinwith a certain counting rate. The input voltage signals of the designed CSA are displayed in the second row. The signals in the third row are related with the double-sampled input voltage. According to the design requirements of the ASIC, the equivalent input charge is selected as 100 fC (the pulse current width is 10 ns and amplitude is 10 μA). The circuit can follow the changes of the input signal well when the frequency of the input signal less than 1 MHz.

Fig.13 Power supply rejection ratio of reference current source circuit

Fig.14 Simulation of counting rate

5.2 Dynamic range and gain switching

The relationship between CSA output voltage and input charge is shown in Fig.15. The dynamic range in Fig.15 can be obtained by linear fitting of the output and input charges of the CSA. Among them, the conversion gain in the range of 5-165 fC is 1.96 V/pC. While switching to a medium gain of 0.39 V/pC in the range of 166-760 fC. When the input charge quantity exceeding 760 fC and less than 8.6 pC, the lowest gain (94 mV/pC) channel will be selected.

Fig.15 Relationship between CSA output voltage and input charge

The integral nonlinearity in each gain range is calculated separately. The integral nonlinearity evaluated for high gain range and medium gain is about 0.052% and 0.031%, respectively. The nonlinearity in low gain stage becomes very large because the designed front-end readout ASIC is close to the saturation state when the detector signal charge quantity arrives to the level of 8.0 pC and the above. The integral nonlinearity in the low gain range decreases to about 1.01% when the detector output signal charge is ≤8.0 pC.

5.3 Random signal response

Generally speaking, the characteristic of the nuclear signal received by the detector is random. As thus, the signal processed by the front-end readout circuit also presents certain random characteristics. To this end, the response of the designed front-end readout ASIC to the typical input random signals setting is simulated, and the results are shown in Fig.16-19. In which a group of pulse signals with different intervals, different pulse widths, and different pulse amplitudes are used for testing, and each group contains three pulses.

Fig.16 Transient simulation result of radom signal with equal interval, same width, and same current amplitude

Fig.17 Transient simulation result of radom current pulse signal with non-equal interval, same pulse width and same pulse current amplitude

Fig.16 presents the output results of equal-interval pulses. The pulse is set with 20 ns width and a 20 μA current amplitude, respectively. The four lines in Fig.16 from top to bottom are the reset signal, the input signal, the output voltage of D trigger’s port D1, and the output voltage of the CSA, respectively. It can be seen that the three input signals all make D1act, that is, they all automatically adopt medium gain. It is worth noting that the output voltage of the first pulse is slightly lower than the following two. The reason is that the switch connected to the second feedback capacitor does not have an infinite turn-off resistance. When the first pulse arriving and being amplified by the preamplifier, a certain voltage drop is generated on the switch during the discharge process, and a certain charge is accumulated. When the next two pulses come, the accumulated charge is transferred to the capacitor connected with the switch when it is switched on, which leads to the above phenomenon. While the accumulated charge is transferred to the connected capacitor when two pulses are accompanied by a moment with the switch is turned on.

Fig.18 Transient simulation results of input radom signal with different widths, pulse current amplitudes for all input signals setting as 20 μA

The pulses shown in Fig.17 are similar to those in Fig.16. However, it presents that the output of the first pulse is not captured by the preamplifier because of the falling within the reset interval. The output of the other two pulses is the same as the first set of group.

In Fig.18, the amplitude of the pulse current is 20 μA with different pulse widths setting as 20, 40, 10 ns, respectively (the corresponding charge amounts are 400, 800, 200 fC, respectively). The curves displayed in the rows from top to the bottom in sequence respectively represent the reset signal, the input pulse current signal, the output voltage of D trigger’s port D1, the output voltage of D trigger’s port D2and the output voltage of CSA respectively. As results, it can be found that the AGC model can recognize and complete the automatic adjustment of the gain for signals with different amounts of charge.

Fig.19 shows the transient simulation results of input signals with different amplitudes, the current pulse widths are all set as 20 ns. The automatic adjustment of the three-stage gain can be realized normally.

5.4 ENC and power consumption

The equivalent noise charge (ENC) is the conversion of the noise voltage from the non-ideal CSA output to an ideal noiseless CSA input. In this paper, the ENC of the front-end readout ASIC given as follows:

(5)

According to the above analysis, the equivalent noise charge of the charge sensitive preamplifier can be calculated by the following formula:

(6)

The main influence factors on ENC include the thermal noise of the MOS transistor (ENCth), the flicker noise (ENCfl), the leakage current of the detector and the shot noise induced by switch resetting (ENCsh).

Fig.20 Distribution of equivalent noise charge for designed readout ASIC changed with input capacitance

In the post-simulation, the width of the input pulse current is set as 10 ns, the amplitude is 1 μA. Thus, the input chargeQinis 10 fC to measure the output noise voltage and output signal voltage. Scanning the input capacitance can get the change of ENC with the input capacitance (Fig.20). It shows that ENC increases linearly with the increasing input capacitanceCin. The level of the calculated ENC (241.6e-@0 pF) is smaller than the required (500e-). Meanwhile, the ENC is arrived to 2204.1e-(0.35 fC) when the input capacitance is 10 pF. Therefore, the parasitic capacitance of the connection between the detector and the front-end circuit should be reduced as much as possible in order to reduce the circuit noise.

The simulated power consumption distribution of the front-end circuit is shown in Fig.21. To optimize the power dissipation of the front-end circuit, the selected working frequency for the readout ASIC is 1 MHz, the switch reset discharge time sets as 100 ns, and the delay time of input pulse current is selected as 3 μs.Fig.21 shows that the total dissipation of the single channel of the readout ASIC is about 5.36 mW. This means that the specification of the power dissipation satisfies the requirements.

Fig.21 Power consumption of designed single channel readout ASIC changed with time during transient simulation

6 Conclusion

This paper presents a front-end readout ASIC model with variable gain and wide dynamic range designed for the new 3D Si PIN neutron detector, which aims to change the conversion gain by discriminating the output signal of the CSA. The results of the designed front-end readout ASIC show that its dynamic input range arrives to the range of 10 fC-8.0 pC. The integral nonlinearity is less than 1%. The static power consumption is 5.36 mW/channel and the ENC is 241.6e-@0 pF. The post-simulation results of multiple signal inputs show that the front-end circuit can switch the gain normally under different input signals.

For the future work, trying to adjust the gain by the filter shaping time, and the control signal of the switch is given by the off-chip, so as to obtain higher counting rate and higher signal-to-noise ratio. The problem for the missing count induced by the switch reset with a certain time interval needs to be further improved in future work.