A 5.4mW and 6.1% efficiency fixed-tuned 214GHz frequency doubler with Schottky barrier diodes*

Yao Changfei (姚常飛), Zhou Ming, Luo Yunsheng, Kou Yanan, Li Jiao

(*Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing Electronic Devices Institute, Nanjing 210016, P.R.China)(**Department of Microwave and Millimeter Wave Modules, Nanjing Electronic Devices Institute, Nanjing 210016, P.R.China)

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A 5.4mW and 6.1% efficiency fixed-tuned 214GHz frequency doubler with Schottky barrier diodes*

Yao Changfei (姚常飛)**, Zhou Ming**, Luo Yunsheng**, Kou Yanan**, Li Jiao**

(*Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing Electronic Devices Institute, Nanjing 210016, P.R.China)(**Department of Microwave and Millimeter Wave Modules, Nanjing Electronic Devices Institute, Nanjing 210016, P.R.China)

A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50μm thick quartz substrate. Diode embedding impedance is found by full-wave analysis with lumped port to model the nonlinear junction for impedance matching without the need of diode equivalent circuit model. All the matching circuit is designed “on-chip” and the multiplier is self-biasing. To the doubler, a conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and the typical measured efficiency is 4.5% in 200～225GHz.

frequency doubler, planar schottky diode, quartz substrate, efficiency

0 Introduction

A Terahertz band spans the gap between infrared and millimeter waves. This portion of electromagnetic spectrum has attracted great commercial and scientific interest. Because Terahertz wave sources can be used for a variety of applications, such as molecular spectroscopy, atmospheric remote sensing, scaled radar range systems, sensing and monitoring of chemical and biological molecules, increased security for point-to-point communications as well as covert battlefield communications, the wide spread utilization of Terahertz band is very slow, and the primary reason is due to the lack of broad band, high power, high stability and compact sources. The existing millimeter and Terahertz wave solid state sources technology can be classified into oscillators, multipliers and amplifiers. The power of the two terminal devices like GUNN and IMPATT decreases dramatically at frequencies higher than 100GHz[1-3]. Three terminal devices like HBT, HEMT and lately developed SiGe CMOS and BiCOMS technology also have the problem of low output power and high phase noise[4-10]. The output power of amplifiers is also lower than that of multipliers and usually power amplifiers are unavailable. The QCL sources are limited in output power and require cryogenic cooling. In order to generate high efficiency, high output power, broad band, low noise, tunable and compact THz sources, frequency multiplication is still a very effective way to realize it now[11-16].

There are two types of diodes for frequency multiplying, Schottky barrier diodes and heterostructure barrier varactor diodes (HBVs). HBVs have the characteristic of symmetric capacitance-voltage (C-V) and anti-symmetric current-voltage (I-V). These characteristics simplify odd-order frequency multiplier design because no even-order harmonics are generated by the device[15]. Furthermore, DC bias is not needed because the capacitance modulation region is centered at zero-bias. Commonly, Schottky diodes are superior to HBVs at millimeter and submillimeter wave frequency for high output power and efficiency. Therefore, in this paper, hybrid integrated balanced frequency doubler circuit is designed with Schottky diodes, whereby odd-order modes are suppressed and facilitate the upconversion of the input frequency to higher harmonics. To the designed doubler, the highest conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and output power is higher than 4.1mW in 210～225GHz, the typical measured efficiency is 4.5% in 200～225GHz.

1 Circuit design

The design process of the doublers is presented as follows: First, the physical structure based diode model is setup in HFSS and its S-parameters are exported for harmonic balance analysis (HBA) in ADS to find optimum diode embedding impedance. Second, the doubler circuit is divided into several parts, where each part is simulated and optimized individually. All passive networks, such as low pass filter, E-plane waveguide to microstrip transition, input and output matching networks, and passive part of diodes are analyzed by EM simulators. The different parts are then combined and optimized together for required multiplying efficiency. The exported S-parameters of the optimized complete circuit are used for harmonic balance analysis in ADS. If the simulation results are not satisfied, the circuit should be re-optimized to fulfill the design specification, otherwise, the circuit parameters are exported for manufacturing.

1.1 Diode embedding impedances

Usually, balanced multipliers are preferred for the simplified idle circuits design and higher efficiency. State-of-the-art performance has been achieved by balanced frequency doubler with Erickson’s scheme[11]. As described in Fig.1, a flip chip planar Schottky varactor chip with four diodes integrated in antiseries configuration is adopted, which can enhance the power handling capability due to the increasing number of the applied diode, in which each arm of the diodes are bonded to the metal channel. The reverse bias is applied to the diodes from the center line connected to the cathodes of the two arms. Input signals are out-of-phase to diode chip, the generated even harmonic signals are in-phase at output port, and the generated odd harmonic signals are out-of-phase and can’t propagate to the output port. Therefore, the multiply circuit can realize balanced even harmonic frequency multiplication. The following formulas describe the nonlinearI-Vrelationshipsofthedoublerwhichoccurstotheconventionalandreversepolarityofthesourcevoltagerespectively.ItcanbeconcludedfromEq.(3)thattheoutputtotalcurrentincludessecondharmonicoftheinputfrequencyonly,therefore,thecircuitrealizessecondharmonicmultiplyingonly.

I1=-f(-V)

=aV-bV2+cV3-dV4+eV5+…

(1)

I2=f(V)=aV+bV2+cV3+dV4+eV5+…

(2)

I=I2-I1=2bV2+2cV4+…

(3)

Tobeabletoaccuratelypredicttheoptimumembeddingimpedances,addingtheinfluenceofthediodechipparasitic,afull3DEMsimulationofthediodechipisanalyzedwithinternalcoaxialorlumpedporttomodeltheSchottkyjunction.TheS-parameterfileofthediodechipisexportedforembeddingimpedancesdiscussioninADS.ThediodeSchottkyjunctionismodeledbySPICEparameters,whichareextractedbymeasuredI-Vcurve,andzerobiasvoltagejunctioncapacitancecanbecalculatedbyjunctionarea.ThediodeSPICEparametersareCjo=0.02pF,Is=1.5×10-13A,Rs=5Ω,n=1.15.ByrunningHBAinADS,thediodeoptimumimpedanceofinputpumpfrequencyandoutputsecondharmonicfrequencyarefound(Zfp= 10+j×41,Z2fp= 16+j×24).Thevalueofimpedancewillbeusedthereaftertosynthesizethedoubler.

Fig.1 Doubler complete model in HFSS

1.2 Circuit optimization

In the doubler circuit, the diodes are in series across the input waveguide and are parallel coupled into the output waveguide. The incident signal would feed the anti-series diode array in a balanced mode (TE10) which is dominant mode in the input rectangular waveguide, and the input back short (L1) is turned to maximum transmission of pump signals to diode, with following reduced-width waveguide channel to sufficiently cut off the input TE10mode[12]. The output section consists of the waveguide-microstrip transition, and the suspended microstrip quartz circuit which can be classified into two parts. The first part next to the varactor chip (L1) is characterized by quasi-coaxial part, while the second part which forms the output embedding circuit is suspended strip line. The excited second harmonic component is radiated in the unbalanced wave mode TEM, passing through the quasi-coaxial region between the varactor chip terminal and the input back-short, and then coupled into the output waveguide port with a succession of matching transmission lines. Therefore, effective isolation between the input and the output radiations can be achieved due to the mode orthogonal, and the input and output circuit can be designed, respectively. When the subcircuits have been optimized, the complete doubler circuit is simulated. The seven port S-parameters of this simulation are extracted and then combined with nonlinear diode to predict the multiply efficiency in circuit simulator, as shown in Fig.2. This process is repeated for further complete optimization of the doubler multiply efficiency.

Fig.2 Doubler global optimization

2 Experimental results

The doubler circuit substrate is an ultra thin quartz substrate with thickness of 0.05mm, and the dielectric constant of 3.78. The circuit is mounted to the block with silver epoxy and the area is 3.3×0.5mm2. The split block is manufactured by brass and electroplate with gold. The doubler split block photo is given in Fig.3.

Fig.3 Photo of the doubler

The doubler measurement setup is presented in Fig.4. The input pump power of doublers is provided by BWO-W signal generator of ELVA-1, and it is precisely calibrated by millimeter and submillimeter power meter PM-4. As shown in Fig.5 and Fig.6, the highest measured conversion efficiency of 6.1% and the output power of 5.4mW are measured at 214GHz with the input power of 88mW, and the output power is higher than 4.1mW in 210～225GHz, and the typical measured efficiency is 4.5% in 200～225GHz. The maximum deviation between measured and simulated efficiency is about 3%, which may be caused by minor errors of diode physical dimension in simulation because the exact diode dimension is commonly unavailable, and the diode series resistance in simulation should be corrected empirically to achieve good agreement between calculated and experimental results. The unbalance of diode four anodes, block manufacture errors and the mounting alignment accuracy of the diode can also affect the performance of the doublers. It can be found from Fig.7 that the measured return loss is about -7dB and response is flat.

Fig.4 Measurement setup of the doubler

Table 1 illustrates some reported multipliers performance. Compared with Ref.[14], the proposed multiplier average value is superior, while bandwidth and efficiency are better than that of Ref.[15]. Compared to the multiplier in Ref.[16], which is optimized for fixed frequency; the proposed doubler has the advantage of wider bandwidth. Obviously, the designed doubler achieves the same level as reported papers.

Fig.5 Measured output power versus input power

Fig.6 Multiply efficiency

3 Conclusions

A 5.4mW and 6.1% efficiency fixed-tuned 214GHz frequency doubler is analyzed and designed with planar barrier Schottky diode, respectively. Full-wave analysis is carried out to find diode embedding impedances with lumped port to model the nonlinear junction. An iterative “divide and combine” design approach is adopted for circuit optimization. The optimized exported S-parameters of the circuit are used for multiplying efficiency analysis. To the doubler, the highest measured conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and output power is higher than 4.1mW in 210～225GHz, the typical measured efficiency is 4.5% in 200～225GHz. The doubler is compact, fixed-turned, and high efficiency, which is very attractive for test instrument, frequency sources and corresponding application systems.

Table 1 Performance comparison

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Yao Changfei, born in 1982. He received his Ph.D degree from Southeast University in 2010. He now serves as a senior engineer in Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute. His work focuses on millimeter and submillimeter wave circuit and systems.

10.3772/j.issn.1006-6748.2015.01.012

*Supported by the 12th Five-year Defense Pre-research Fund of China (No. 51308030509).

*To whom correspondence should be addressed. E-mail: yaocf1982@163.comReceived on Sep. 2， 2013