Special Section on Energy-Efficient Technologies: NoC Circuits, Architectures, and Systems

Xiao-Hang Wang

Special Section on Energy-Efficient Technologies: NoC Circuits, Architectures, and Systems

Xiao-Hang Wang

Energy consumption has been one of the major challenges and concerns for the electronic devices design, especially in high-performance multi- and many-core systems. A highly integrated many-core chip is prone to be extremely high-power consumption that exceeds the chip’s power budget set leaded by cooling, packaging and/or the capacity of the power supply. When this situation happens, various parts of the many-core chip will have to be deliberately switched off (darkened) so that the chip is still in compliance with its power budget, which is referred as“dark silicon”. Therefore, the research on energy efficient computing is a current trend and will continue to be an active area in the coming years.1

In connection with the above view, and being invited by JEST, we have proposed this special issue on energy efficient computing: network-on-chip (NoC) circuits, architectures, and systems. The focus is basically on the architecture, algorithm, implementation, and design methodology of energy-efficient computing systems. We have paid particular attention to the architecture design of energy efficient many-core and NoC systems, which might be the cornerstone of high-performance computing in our opinion.

This special session is opened by a paper on energy-efficient NoC architecture design in the dark silicon era with reconfigurable switches which is written by Teng-Fei Wang. In the dark silicon era, a fraction of the NoC might be turned OFF (i.e., by power gating). The problem is, given a power budget for the NoC, to find the optimal set of routers to be dark (i.e., being turned OFF) so that the overall network performance is the best. To achieve this goal, routers with low workloads are selected to be powered OFF. The configurable switches are used to detour the traffic. Another issue is the leakage power which is highly correlated with temperatures. The configurable switch can bypass certain routers to reduce the dynamic power consumption and thus reduce the temperature.

The second paper realizing energy efficient on-chip communications by exploiting power slacks, studies an energy-efficient or even zero energy routing algorithm for many-core systems by using solar energy and supercapacitors. As solar energy is becoming more popular due to its cleanness, many electronic devices are powered by it, including miniature systems and data center systems. This paper targets an embedded low power many-core system where each router is equipped with a supercapacitor. The supercapacitors can be charged by exploiting the power slacks and they can provide the energy for on-chip communication. The focus is to find an optimal path with the maximum stored energy so as to minimize the electronic energy consumption. A dynamic programmingnetwork is proposed to find the optimal path efficiently with linear time complexity.

The third paper proposes a new latency model for dynamic frequency scaling on network-on-chip fine-grain power budgeting for NoC. As the router workloads might be very different, a smart power budgeting method that could allocate power budgets according to the workload of each router to minimize network latency is necessary. In this paper, the authors focus on the latency modeling, taking into consideration of the per-router frequency scaling. This per-router frequency scaling aware network latency model can be used to allocate power budgets optimally to each router, so as to find a tradeoff between the power consumption and latency.

Besides the conventional NoC systems connected with wirelines, emerging technologies like the surface wave, optical, mm-wave, etc. are getting popular for their low power and latency. The fourth paper, the application aware topology generation for the surface wave networks-on-chip, studies the problem of optimal topology generation for the surface wave based NoC, giving an application’s communication pattern. The generated topologies will explore the latency and power properties of the emerging technology.

The last paper discusses a low-power design of Ethernet data transmission. The network transmission has consumed substantial power and bandwidth in a computer system. This work tries to allocate power budget to each module according to its workload using frequency scaling. And data integrity is also guaranteed in the system.

Finally, as the guest editor of this special issue, I would like to express my gratitude to all the authors for their generous contribution by submitting the manuscripts. In particular, I would like to thank the editorial staff for their countless effort and enormous help throughout the process. And we expect that more and more scientists will be involved in this significant area for our future green life.

Xiao-Hang Wang,Guest EditorGuangzhou Institute of Advanced Technology, Chinese Academy of Sciences, China

Xiao-Hang Wang received the B.Eng. and Ph.D. degrees in communication and electronic engineering from Zhejiang University, Hangzhou in 2006 and 2011, respectively. He is currently an assistant professor at Guangzhou Institute of Advanced Technology, Chinese Academy of Sciences. His research interests include many-core system architecture, NoC system, algorithm design, and energy efficient computing. Dr. Wang was the author of 30+ scientific publications and 2 patents. He serves as the general co-chair of the NoCArc workshop (which is a workshop with the MICRO conference), and the TPC member of international conferences.

Digital Object Identifier: 10.3969/j.issn.1674-862X.2014.04.001