Low Power Design of Pipelined ADC for Power Line Baseband Communication

Beijing Embedded System Key Lab，Beijing University of Technology，Beijing 100124，China

Yang Chen，Xuejing Liu，Mengmeng Fang，Pingfen Lin

1.Introduction

The proposed pipelined ADC is used in single carrier power line communication system.The carrier frequency is 132 KHz and maximum sampling frequency should be supported to 5 MHz .Recently，low-power pipelined ADC design is mainly focused on the following aspects：sample and hold circuit removing technique[1]，op amp sharing[2]，digital background calibration[3].Sample and hold circuit removing configuration is suitable for low frequency application.Digital background calibration technique is useful for high-speed，high resolution and deep submicron process，such as 65 nm[3].For180nm process，as well as low-speed，medium-accuracy pipelined ADC，the power consumed by the digital calibration section is more than the power reduced by relaxing the requirements of analog parts.Op amplifier sharing technology can reduce power consumption and area，but the reduction is limited.Take 2.5bit pre stage for example，in order to achieve the best noise and the power consumption requirements，the sampling capacitance size of adjacent to op amp is reduced four times，so is the power consumption[4].On the other hand，the op amp should be designed in accordance with the requirements of the first stage.Reduced power consumption is just 25% of the power consumed by the first stage.Single sub-stage achieving the greater the number of bits（resolution），the smaller power consumption can be reduced by operational amplifiers sharing technology.Switched op amp technique[5] can save more power about 50%，but it brings to two issues，fast start up and common mode stability.This paper adopts switched op amp ADC structure and proposes the SC bias circuit to solve the fast startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability，according to the characteristics of the low frequency input signal in the power line baseband applications，the sample and hold circuit is removed to further reduce power consumption.

The ADC design is discussed in section 2，simulation results are shown in section 3，and conclusions are drawn in section 4.

2.ADC Architecture and Implementation

The overall architecture of the proposed ADC is shown in Fig.1.The core is composed of four 2.5-bit

sub stages and a 2-bit flash ADC.SHA is removed.The absence of SHA would induce an offset error at the comparator input due to the aperture error.The issue is critical in high frequency input[6].For carrier frequency which is 132 KHz，SHA is not necessary.In addition，the sampling switch capacitor circuits are carefully designed to reduce the mismatch of the time constant between the signal paths in MDAC and comparators.The current bias circuit is included in each stage.DEC is the digital error correction module and ClkGen is the clock source of two nonoverlapping complementary clocks for the core.

2.1 Sub Stage Configuration

Taken noise and power into account，the size of the sampling capacitance of adjacent to op amp is reduced four times[4]，and power consumption is reduced four times too.The op amp of first stage is shown in Fig.2.Folded cascade and gain enhanced structure is used to meet the system requirements on the op amp DC gain.

Switches S1，S2，S3，are controlled by clock PD，and S4，S5 are controlled by clock PD_N，S6，S7 are complementary switches.When the op amp is in the sampling phase，PD is high，S1-S5 are off to disable any flow of current and S6-S7 are on to connected the ports VOP，VON to VCM.On the other phase，S1-S5 are on and S6-S7 are off to let the op amp amplifying.The difference between this configuration and normal one is that quiescent current exists in normal configuration in sampling phase.The advantage of normal one is that it does no need to startup before the amplification，but it consumes a large amount of quiescent current.Quiescent current is zero in the new configuration in sampling phase，but the new structure brings to two issues，fast start up and common mode stability.The switch-capacitor current bias and common mode feedback circuits are employed to solve the issues and they will be detailed in next section.

2.2 Switch Capacitor Current Bias

As mentioned above，the operational amplifier should startup to establish the quiescent operating point.The process of establishment is the sooner the better，because the differential input signal should be settling at the same time.Startup time is heavily dependent on the biasing circuitry.In principle，the biasing circuit has a static function，but it also needs to startup in a short time to enable dutycycling of this part of the design.Paper[6] gives a solution for fast startup.Circuitry is shown in Fig.3.

When the current mirror is off，Cg is shorted to ground to disable any flow of current.At the same time，a capacitor Cf is pre-charged to VDD.As soon as the current mirror needs to be enabled，Cg is disconnected from the ground and connected to Iref.Also，Cf is reconnected to Cg.By means of charge sharing，Cf will quickly precharge Cg to a working condition，while Iref will still determine the final steady-state operating point.[7].Dependent on the value of Cf，the pre-charge can result in some undershoot or overshoot during startup.Since this effect is dependent on PVT conditions，Cf must be digitally programmable.So，this method increases the complexity of the design and application.

Figure 1.ADC Architecture

Figure 2.First Stage Op Amp Structure

Figure 3.Fast Startup Current Bias

Figure 4.SC Current Bias

Figure 5.Successive Approximation Process of SC Current Bias

Figure 6.CMFB Networks

This work proposed a switchedcapacitor biasing circuit to solve the startup issue，and it’s shown in Fig.4.This method relaxes the ratio of two capacitors，Cf and Cg.

The SC biasing circuit is composed of two parts：a current mirror，and a switch capacitor sampling network.When the sub stage is in the sampling phase，the op amp is turned off as description in part 2.1，at the same time the switches S1，S2 are closed（on），S3 are open（off）， the bias circuit turns on and charges Cf.Charge on the Cg is kept.As soon as the sub stage is in the amplification phase，the switches S1，S2 are off，S3 is on.Charge will redistribute in the capacitor Cf and Cg.After one cycle，

two cycles，

……

N cycles，

Voltage Vx is successive approximation Vbias by means of the geometric sequence，and eventually stabilized in Vbias.The successive approximation process is shown in Fig.5.

Figure 7.Layout of the ADC

Figure 8.FFT spectrum at 132 KHz input

There are two major advantages in SC current bias，first，Cf is charged when the sub stage is in the sampling phase.It has the half cycle to establish a stable state，and charge redistribution can complete immediately in the amplification phase.Second，this circuit does not require precise ratio between the proportion of Cf and Cg，with a charge redistribution process，Cf and Cg of any proportional relationship，can make the voltage Vx stable in VB.In fact，this circuit can be used not only in the ADC but also in any place with the clock.

2.3 CMFB

The process of switch capacitor common-mode feedback has 2 steps，first sensing common-mode voltage at outputs of main op-amp，second comparing it with a reference voltage and returning the feedback signal to bias current source.The 2 st eps can not be done with one CMFB network at the same time，but for commonmode stability feedback should be done in each amplification phase.So，two common-mode feedback networks are adopted.In the first cycle CMFB1 senses common-mode voltage，while CMFB2 compares it with a reference voltage and returns the feedback signal to bias current source.In the next cycle CMFB1 and CMFB2 swap their functions.CMFB networks are shown in Fig.6.CMFB1 is composed of C1-C4，and CMFB2 is composed of C3-C6.C3，C4 is shared.

Similar to the SC current bias described above，the common-mode voltage is successive approximation VCM and eventually stabilized in VCM.

3.Simulation Results

The proposed pipelined ADC is designed in standard 180nm CMOS process.The active area is 650 μm ×500 μm，which is shown in Figure 7.

Figure 8 shows the spectrum of the output 10bit data with the 132K input signal，5M sampling rate.SNDR is 59.6dB SFDR is 75.8dB.

4.Summary

This paper presents 10bit 5MS/s pipelined ADC for single carrier power line communication.It’s a lowpower method by using switched op amp technique to reduce the power consumption，and proposes the SC bias circuit to solve the startup issue of the current bias.Two commonmode feedback networks are employed to solve the problem of common-mode stability.The ADC occupies 650μm×500 μm and consumes an average of 0.6 mA at 1.8V supply voltage.The ADC achieves the FoM 0.22 pJ/step in simulation.

[1]Mer L.Singer.A 55-mW 10-bit 40MSample/s Nyquistrate CMOS ADC[J].IEEE J.Solid-State Circuits,Vol.35,No.3,p.318～325.(2000).

[2]Dong-Young Chang and Un-Ku Moon,“A 1.4V 10-bit 25-Ms/s pipelined ADC using op amp-reset switching technique”,IEEE J.Solid-State Circuits,vol.38,No.8,p.1401-1404.(2003).

[3]Bei Peng.“A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion”,IEEE Trans.Circuit and System II,vol.57,No.11,p.853-857.(2010).

[4]D.W.Cline,P.R.Gray.“A Power Optimized 13-b 5M Samples/s Pipelined Analog-to-Digital Converter in 1.2μm CMOS”,IEEE J.Solid-State Circuits.(1996).

[5]J.Crols and M.Steyaert,“Switched op amp:An approach to realize full CMOS SC circuits at very low supply voltages,”IEEE J.Solid-State Circuits,vol.29,pp.936-942,Aug.(1994).

[6]Pingli Huang.“SHA-Less Pipelined ADC with In situ Background Clock-Skew Calibration”,IEEE J.Solid-State Circuits,vol.46,No.8,p.1893-1903.(2011).

[7]P.Harpe.“A 1.6mW 0.5GHz Open-Loop VGA with Fast Startup and Offset Calibration for UWB Radios”,IEEE ESSCIRC.p.103-106.(2011).