ＣＭＯＳ集成電路瞬態(tài)電流片外電流傳感器電路

摘 要：瞬態(tài)電流（IDD）測(cè)試經(jīng)常被看作是靜態(tài)電流（IDDQ）測(cè)試的替代或補(bǔ)充，特別在深亞微米技術(shù)中，受到越來(lái)越多的關(guān)注。根據(jù)一種基于電荷的瞬態(tài)電流片外電流傳感器電路，并在其基礎(chǔ)上進(jìn)行改進(jìn)并對(duì)兩階多米諾加法器電路進(jìn)行仿真實(shí)驗(yàn)，實(shí)驗(yàn)結(jié)果表明，改進(jìn)后的電路能有效讀取集成電路中的瞬態(tài)電流，從而實(shí)現(xiàn)瞬態(tài)電流的測(cè)試。

關(guān)鍵詞：CMO集成電路；瞬態(tài)電流；有阻開(kāi)路；測(cè)試技術(shù)

Off-chip ransient Current Monitor Circuit of CMO Integrated Circuit

LI Xiangjun，LI Chunming

(College of Information Engineering，Inner Mongolia University of echnology，uhhot，01001，China)

Abstract：ransient current testing(IDD) has been often cited as an alternative or supplement to IDDQ testing ，especially in deep-submicro technologies ，such test technique is noticed by more and more researchersAn off-chip and charge-based transient current monitor circuit is presentedOn the basis ofit，the circuits is improved and simulated for second Domino parallel circuits，experimental results show that the circuit can effectively sense transient current of integrated circuit and hence，perform transient current testing

Keywords：CMO integrated circuits;transient current;resistive open;test technology

隨著芯片特征尺寸的縮小和電路復(fù)雜程度的增加，有阻開(kāi)路和有阻橋接缺陷的數(shù)目也在增加。同時(shí)，隨著器件密度、復(fù)雜性和時(shí)鐘速度的增加，邏輯測(cè)試技術(shù)已不能提供足夠的故障覆蓋率。為了彌補(bǔ)傳統(tǒng)測(cè)試方法的不足，基于靜態(tài)電流（IDDQ）的測(cè)試方法被廣泛使用。然而，隨著深亞微米技術(shù)時(shí)代的到來(lái)，總的靜態(tài)漏電流急劇增加，IDDQ測(cè)試技術(shù)受到嚴(yán)峻挑戰(zhàn)［1-3］，因此，需要尋找新的測(cè)試技術(shù)，而瞬態(tài)電流測(cè)試技術(shù)提供一個(gè)很好的替代或補(bǔ)充。這種測(cè)試方法能夠檢測(cè)傳統(tǒng)測(cè)試和IDDQ測(cè)試所不能檢測(cè)的缺陷［4］。